Transistor display panel, manufacturing method thereof, and display device including the same

ABSTRACT

A transistor display panel including: a driving voltage line and a first electrode disposed on a substrate; a semiconductor overlapping the first electrode; and an electrode layer overlapping the semiconductor, the electrode layer including a drain electrode, a gate electrode, and a source electrode. The first electrode and the semiconductor are connected through the source electrode.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Reissue Application of U.S. patent applicationSer. No. 15/452,602, filed on Mar. 7, 2017, issued on Oct. 15, 2019 asU.S. Pat. No. 10,446,591, and claims priority from and the benefit ofKorean Patent Application No. 10-2016-0042786, filed on Apr. 7, 2016,which is hereby incorporated by reference for all purposes as if fullyset forth herein.

BACKGROUND

Field

Exemplary embodiments relate to a transistor display panel, a method formanufacturing thereof, and a display device including the same.

Discussion of the Background

A transistor included in various electronic devices, such as a displaydevice, includes a gate electrode, a source electrode, a drainelectrode, and a semiconductor. The transistor is used as a switchingelement, a driving element, and the like in the display device.

The semiconductor material used in the transistor is an important factorin determining characteristics of the transistor. The semiconductortypically includes silicon (Si). The silicon is divided into amorphoussilicon and polysilicon according to a crystallization type, wherein theamorphous silicon has a simple manufacturing process but has low chargemobility such that there is a limit for manufacturing a high performancethin film transistor, and the polysilicon has high charge mobility but aprocess of crystallizing the silicon is required such that themanufacturing cost is increased and the process is complicated.Recently, studies regarding a thin film transistor using an oxidesemiconductor with a higher on/off ratio and carrier mobility than theamorphous silicon, and lower cost and higher uniformity thanpolycrystalline silicon, have progressed.

The above information disclosed in this Background section is only forenhancement of understanding of the background of the inventive concept,and, therefore, it may contain information that does not form the priorart that is already known in this country to a person of ordinary skillin the art.

SUMMARY

Exemplary embodiments are directed to improving characteristics of atransistor, and reducing a number of masks and process steps in a methodfor manufacturing a transistor display panel.

Additional aspects will be set forth in the detailed description whichfollows, and, in part, will be apparent from the disclosure, or may belearned by practice of the inventive concept.

An exemplary embodiment discloses a transistor display panel including:a driving voltage line and a first electrode disposed on a substrate; asemiconductor disposed on the substrate and overlapping the firstelectrode; and an electrode layer overlapping the semiconductor, theelectrode layer including a drain electrode, a gate electrode, and asource electrode, and the first electrode and the semiconductor may beconnected through the source electrode.

The semiconductor includes a drain region, a channel, and a sourceregion, and the drain region and the driving voltage line may beconnected through the drain electrode.

The source region and the first electrode may be connected through thesource electrode.

The drain electrode, the gate electrode, and the source electrode may bedisposed in the same layer.

The first electrode and the driving voltage line may be disposed in thesame layer.

The transistor display panel may further include a first insulatinglayer covering the driving voltage line and the first electrode, and asecond insulating layer covering the semiconductor, wherein the firstinsulating layer and the second insulating layer may include a firstcontact hole connecting the first electrode and the source electrode anda second contact hole connecting the driving voltage line and the drainelectrode, and the second insulating layer may include a third contacthole connecting the source region and the source electrode and a fourthcontact hole connecting the drain region and the drain electrode.

The second insulating layer may be disposed on an entire surface of thesubstrate.

An exemplary embodiment also discloses a display device including: adriving voltage line and a first electrode disposed on a substrate; asemiconductor disposed on the substrate and overlapping the firstelectrode; an electrode layer overlapping the semiconductor, andincluding a drain electrode, a gate electrode, and a source electrode,and a pixel electrode disposed on the electrode layer. The firstelectrode and the semiconductor may be connected through the sourceelectrode, and each of the pixel electrode and the first electrode maybe connected with the semiconductor through the source electrode.

The display device may further include a first capacitor electrodedisposed on the substrate, and a second capacitor electrode disposed onthe first capacitor electrode. The first capacitor electrode may beintegrally connected with the first electrode, and the second capacitorelectrode may be integrally connected with the gate electrode.

The semiconductor includes a drain region, a channel, and a sourceregion, the drain region and the driving voltage line may be connectedthrough the drain electrode, and the source region and the firstelectrode may be connected through the source electrode.

The display device may further include a first insulating layer coveringthe driving voltage line and the first electrode, and a secondinsulating layer covering the semiconductor. The first insulating layerand the second insulating layer may include a first contact holeconnecting the first electrode and the source electrode and a secondcontact hole connecting the driving voltage line and the drainelectrode, and the second insulating layer may include a third contacthole connecting the source region and the source electrode and a fourthcontact hole connecting the drain region and the drain electrode.

An exemplary embodiment also discloses a method for manufacturing atransistor display panel including: depositing a first conductivematerial on a substrate and patterning the first conductive material toform a driving voltage line and a first electrode; forming asemiconductor on the substrate having the driving voltage line and thefirst electrode; and depositing a second conductive material on thesubstrate having the semiconductor and patterning the second conductivematerial to simultaneously form a drain electrode, a gate electrode, anda source electrode.

The method may further include forming a first insulating layer on thesubstrate having the driving voltage line and the first electrode,forming a second insulating layer on the substrate having thesemiconductor, and etching the first insulating layer and the secondinsulating layer to form a first contact hole exposing the firstelectrode and a second contact hole exposing the driving voltage line.

The method may further include etching the second insulating layer toform a third contact hole and a fourth contact hole exposing thesemiconductor.

The transistor display panel according to the inventive concepts canimprove various performance characteristics of the transistor, such asan output saturation characteristic. Further, according to a process formanufacturing the transistor display panel of an exemplary embodiment,the numbers of masks used and process steps can be reduced, therebyreducing the manufacturing cost.

The foregoing general description and the following detailed descriptionare exemplary and explanatory and are intended to provide furtherexplanation of the claimed subject matter.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the inventive concept, and are incorporated in andconstitute a part of this specification, illustrate exemplaryembodiments of the inventive concept, and, together with thedescription, serve to explain principles of the inventive concept.

FIG. 1 is a top plan view of a transistor display panel according to anexemplary embodiment.

FIG. 2A is a cross-sectional view taken along line II-II′ of FIG. 1 .

FIG. 2B is a cross-sectional view taken along line III-III′ of FIG. 1 .

FIG. 3 , FIG. 4 , FIG. 5 , FIG. 6 , FIG. 7 , and FIG. 8 arecross-sectional views showing a method for manufacturing of a transistordisplay panel according to an exemplary embodiment.

FIG. 9 is an equivalent circuit diagram of one pixel of a display deviceaccording to an exemplary embodiment.

FIG. 10 is a cross-sectional view of a display device according to anexemplary embodiment.

FIG. 11 is a cross-sectional view of a display device according toanother exemplary embodiment.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

In the following description, for the purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of various exemplary embodiments. It is apparent, however,that various exemplary embodiments may be practiced without thesespecific details or with one or more equivalent arrangements. In otherinstances, well-known structures and devices are shown in block diagramform in order to avoid unnecessarily obscuring various exemplaryembodiments.

In the accompanying figures, the size and relative sizes of layers,films, panels, regions, etc., may be exaggerated for clarity anddescriptive purposes. Also, like reference numerals denote likeelements.

When an element or layer is referred to as being “on,” “connected to,”or “coupled to” another element or layer, it may be directly on,connected to, or coupled to the other element or layer or interveningelements or layers may be present. When, however, an element or layer isreferred to as being “directly on,” “directly connected to,” or“directly coupled to” another element or layer, there are no interveningelements or layers present. For the purposes of this disclosure, “atleast one of X, Y, and Z” and “at least one selected from the groupconsisting of X, Y, and Z” may be construed as X only, Y only, Z only,or any combination of two or more of X, Y, and Z, such as, for instance,XYZ, XYY, YZ, and ZZ. Like numbers refer to like elements throughout. Asused herein, the term “and/or” includes any and all combinations of oneor more of the associated listed items.

Although the terms first, second, etc. may be used herein to describevarious elements, components, regions, layers, and/or sections, theseelements, components, regions, layers, and/or sections should not belimited by these terms. These terms are used to distinguish one element,component, region, layer, and/or section from another element,component, region, layer, and/or section. Thus, a first element,component, region, layer, and/or section discussed below could be termeda second element, component, region, layer, and/or section withoutdeparting from the teachings of the present disclosure.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper,” and the like, may be used herein for descriptive purposes, and,thereby, to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the drawings. Spatiallyrelative terms are intended to encompass different orientations of anapparatus in use, operation, and/or manufacture in addition to theorientation depicted in the drawings. For example, if the apparatus inthe drawings is turned over, elements described as “below” or “beneath”other elements or features would then be oriented “above” the otherelements or features. Thus, the exemplary term “below” can encompassboth an orientation of above and below. Furthermore, the apparatus maybe otherwise oriented (e.g., rotated 90 degrees or at otherorientations), and, as such, the spatially relative descriptors usedherein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments and is not intended to be limiting. As used herein, thesingular forms, “a,” “an,” and “the” are intended to include the pluralforms as well, unless the context clearly indicates otherwise. Moreover,the terms “comprises,” “comprising,” “includes,” and/or “including,”when used in this specification, specify the presence of statedfeatures, integers, steps, operations, elements, components, and/orgroups thereof, but do not preclude the presence or addition of one ormore other features, integers, steps, operations, elements, components,and/or groups thereof.

Various exemplary embodiments are described herein with reference tosectional illustrations that are schematic illustrations of idealizedexemplary embodiments and/or intermediate structures. As such,variations from the shapes of the illustrations as a result, forexample, of manufacturing techniques and/or tolerances, are to beexpected. Thus, exemplary embodiments disclosed herein should not beconstrued as limited to the particular illustrated shapes of regions,but are to include deviations in shapes that result from, for instance,manufacturing. The regions illustrated in the drawings are schematic innature and their shapes are not intended to illustrate the actual shapeof a region of a device and are not intended to be limiting.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this disclosure is a part. Terms,such as those defined in commonly used dictionaries, should beinterpreted as having a meaning that is consistent with their meaning inthe context of the relevant art and will not be interpreted in anidealized or overly formal sense, unless expressly so defined herein.

A transistor display panel according to an exemplary embodiment will bedescribed with reference to FIG. 1 and FIG. 2 .

FIG. 1 is a top plan view of a transistor display panel according to anexemplary embodiment, FIG. 2A is a cross-sectional view taken along lineII-II′ of FIG. 1 , and FIG. 2B is a cross-sectional view taken alongline III-III′ of FIG. 1 .

Referring to FIG. 1 , FIG. 2A, and FIG. 2B, a transistor display panelaccording to an exemplary embodiment includes a substrate 110, and aplurality of transistor Qs and Qd positioned on the substrate 110

The transistors Qs and Qd may be transistors of the display device. Forexample, when the display device is an organic light emitting diodedisplay, the transistors may be a driving transistor Qd and a switchingtransistor Qs positioned in a pixel area.

In the drawings, a first direction D1 and a second direction D2 areperpendicular to each other, and are parallel to a horizontal section ofthe substrate 110. A structure shown when observing the surface formedby the first direction D1 and the second direction D2 is referred to asa plane structure.

Further, a third direction D3 is perpendicular to the first and seconddirections D1 and D2 and is parallel to a vertical section of thesubstrate 110. The third direction D3 may be mainly represented in thecross-sectional structure, and is referred to as a cross-sectionaldirection. In the cross-sectional structure, if a constituent element ispositioned on any other constituent element, it means that twoconstituent elements are arranged in the third direction D3, and otherconstituent elements may be positioned between the two constituentelements.

Referring to FIG. 2A, the driving transistor Qd includes a drivingvoltage line 172 and a first electrode 124 positioned on the substrate110, a first insulating layer 111 covering the driving voltage line 172and the first electrode 124, a semiconductor 130 positioned on the firstinsulating layer 111, a second insulation layer 140 positioned on thesemiconductor 130, and an electrode layer 150 positioned on the secondinsulating layer 140.

The substrate 110 may be a substrate including an organic material, aninorganic material, glass, or a metal such as stainless steel.

On the substrate 110, a driving voltage line 172 for transferring adriving signal and a first electrode 124 are spaced apart from eachother by a predetermined interval. In this case, the first electrode 124is positioned to overlap the semiconductor 130 described below.Accordingly, the first electrode 124 can serve as a light blocking film.That is, the first electrode 124 prevents external light from reachingthe semiconductor 130, thereby preventing deterioration of thecharacteristics of the semiconductor 130 and controlling a leakagecurrent of the transistor.

Further, the driving voltage line 172 and the first electrode 124 may beformed with a conductive material such as a metal, and may be formed asa single layer or as multiple layers (multilayer).

The driving voltage line 172 and the first electrode 124 are positionedat the same layer. As described, according to this disclosure, since thedriving voltage line 172 and the first electrode 124 are positioned atthe same layer, they can be simultaneously formed by the same process,so that the manufacturing process can be simplified.

Next, the first insulating layer 111 covering the driving voltage line172 and the first electrode 124 is positioned on the substrate 110.

The first insulation layer 111 functions to protect the semiconductor130 and improve the characteristics of the semiconductor 130 bypreventing permeation of an impurity to the semiconductor 130 from thesubstrate 110. Accordingly, the first insulating layer 111 may bereferred to as a “buffer layer”.

In this case, the first insulating layer 111, for example, may have athickness of about 3000 Å to about 5000 Å.

The first insulating layer 111, for example, may include an inorganicinsulation material such as a silicon oxide (SiO_(x)), a silicon nitride(SiN_(x)), aluminum oxide (Al₂O₃), hafnium oxide (HfO₃), yttrium oxide(Y₂O₃), and the like.

In addition, the first insulation layer 111 may be formed as a singlelayer or as multiple layers (multilayer). In further detail, when thefirst insulation layer 111 is formed as a double layer, a lower layermay include a silicon nitride (SiN_(x)) and an upper layer may include asilicon oxide (SiO_(x)).

The semiconductor 130 overlapping the first electrode 124 is positionedon the first insulating layer 111. The semiconductor 130 includes achannel 131 overlapping a gate electrode 151, and a source region 133and a drain region 135 positioned at respective sides of the channel131.

When a gate-on voltage is applied to the gate electrode 124, the sourceregion 133 and the drain region 135 may be determined depending on adirection of carriers that flow through the channel 131, and thecarriers flow to the drain electrode 135 from the source region 133.Thus, when the transistor TR operates, electrons flow to the drainregion 135 from the source region 133 in an n-type transistor, and holesflow to the drain region 135 from the source region 133 in a p-typetransistor.

In this case, the source region 133 may be electrically connected withthe pixel electrode 191 and the first electrode 124 of the displaydevice through a source electrode 153. Further, the drain region 135 maybe electrically connected with the driving voltage line 172 through adrain electrode 155.

The channel 131, the source region 133, and the drain region 135 mayinclude the same material. For example, the channel 131, the sourceregion 133, and the drain region 135 may respectively include the sameoxide. Such a metallic oxide may exemplarily include an oxide of a metalsuch as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti),and the like, or a combination of a metal such as zinc (Zn), indium(In), gallium (Ga), tin (Sn), titanium (Ti), and the like, and an oxidethereof. In further detail, the oxide may include at least one of zincoxide (ZnO), zinc-tin oxide (ZTO), zinc-indium oxide (ZIO), indium oxide(InO), titanium oxide (TiO), indium-gallium-zinc oxide (IGZO), andindium-zinc-tin oxide (IZTO). Further, the channel 131, the sourceregion 133, and the drain region 135 may include a semiconductormaterial, such as polysilicon.

A carrier concentration of the source region 133 and the drain region135, which are conductors, is different from that of the channel 131.For example, when the carrier concentration of the channel 131 is, forexample, 10¹⁸/cm³ or less, the carrier concentration of the sourceregion 133 and the drain region 135 may be 10¹⁸/cm³ or more. Inaddition, a gradient where the carrier concentration is graduallychanged may be formed at a boundary between the source region 133 andthe channel 131 or a boundary between the drain region 135 and thechannel 131.

Further, the source region 133 and the drain region 135 may include amaterial that is reduced from an oxide semiconductor included in thesemiconductor 130. For example, the source region 133 and the drainregion 135 may further include at least one of fluorine (F), hydrogen(H), and sulfur (S) in addition to the oxide semiconductor included inthe semiconductor 130. At least one of fluorine (F), hydrogen (H), andsulfur (S) included in the source region 133 and the drain region 135may have a concentration of 10¹⁵/cm³ or more. A gradient where aconcentration of at least one of fluorine (F), hydrogen (H), and sulfur(S) is gradually changed may exist at a boundary between the sourceregion 133 and the channel 131 or a boundary between the drain region135 and the channel 131. The source region 133 and the drain region 135may be formed by making the oxide semiconductor that forms thesemiconductor 130 conductive using plasma treatment and the like. Forexample, the oxide semiconductor may be made conductive byplasma-treating the oxide semiconductor under a hydrogen gas atmosphereand dispersing hydrogen into the oxide semiconductor such that thesource region 133 and the drain region 135 can be formed.

Next, the second insulating layer 140 is positioned on the semiconductor130. The second insulation layer 140 may be a single layer or multiplelayers (multilayer). When the second insulation layer 140 is formed as asingle layer, the second insulation layer 140 may include an insulationmaterial such as a silicon oxide (SiO_(x)), a silicon nitride (SiN_(x)),a silicon oxynitride (SiON), aluminum oxide (Al₂O₃), hafnium oxide(HfO₃), yttrium oxide (Y₂O₃), and the like. Further, when the secondinsulation layer 140 is formed as a multilayer, a lower layer thatcontacts the semiconductor 130 may include an insulation oxide such as asilicon oxide (SiO_(x)), aluminum oxide (Al₂O₃), hafnium oxide (HfO₃),yttrium oxide (Y₂O₃), and the like to improve an interface property ofthe semiconductor 130 and prevent permeation of an impurity into thesemiconductor 130, and at least one layer that is formed above thesemiconductor 130 may include various insulation materials such as asilicon oxide (SiO_(x)) and a silicon nitride (SiN_(x)).

The second insulating layer 140 may be formed to have a thickness lessthan the first insulating layer 111. That is, the second insulatinglayer 140, for example, may have a thickness of about 500 Å to about1500 Å.

Further, in this exemplary embodiment, the second insulating layer 140may be formed on the entire surface of the substrate 110, and the secondinsulating layer 140 may be referred to as a “gate insulation layer”. Ifthe second insulating layer 140 is formed only on the portioncorresponding to the gate electrode 151, the transistor may be damageddue to a short circuit occurring between the gate electrode 151 and thesemiconductor 130. Accordingly, the second insulating layer 140 may beformed on the entire surface of the substrate 110.

The first insulating layer 111 and the second insulating layer 140 mayinclude a first contact hole 163 connecting the first electrode 124 andthe source electrode 153, and a second contact hole 165 connecting thedriving voltage line 172 and the drain electrode 155.

Further, the second insulating layer 140 may include a third contacthole 143 connecting the source region 133 and the source electrode 153,and a fourth contact hole 145 connecting the drain region 135 and thedrain electrode 155.

Next, the electrode layer 150 including the drain electrode 155, thegate electrode 151, and the source electrode 153 is positioned on thesecond insulating layer 140. The drain electrode 155, the gate electrode151, and the source electrode 153 are spaced apart from each other atthe same layer, and the drain electrode 155 and the source electrode 153are positioned at opposite sides of the gate electrode 151.

As described above, according to this exemplary embodiment, since thedrain electrode 155, the gate electrode 151, and the source electrode153 are positioned at the same layer, no additional insulating filmformation and contact hole formation steps are required to form them,and the number of process steps and the number of masks required can bereduced. In addition, in comparison with the case where the drainelectrode 155, the source electrode 153, and the gate electrode 151 arepositioned at different layers, it is possible to prevent damage of thesemiconductor due to etching since the etching depth in the step offorming the contact hole for electrically connecting the drain electrode155 and the source electrode 153 to the semiconductor can besignificantly reduced.

In the transistor display panel according to this exemplary embodiment,the first electrode 124 and the semiconductor 130 are electricallyconnected through the source electrode 153. In further detail, the firstelectrode 124 is connected with the source electrode 153 through thefirst contact hole 163, and the source electrode 153 is connected withthe source region 133 through the third contact hole 143.

Further, the driving voltage line 172 is connected with the drainelectrode 155 through the second contact hole 165, and the drainelectrode 155 is connected with the drain region 135 through the fourthcontact hole 145.

The first electrode 124 may receive a bias rather than beingelectrically connected to the source region 133. Thus, when a fixed biasis applied to the semiconductor 130, the output saturationcharacteristic of the transistor can be improved, and for example, theoutput current of the transistor can be less affected by a sourcevoltage or a drain voltage in the saturation area of the transistor.Further, the first electrode 124 may be in an electrically floated staterather than being electrically connected to the source region 133 orreceiving a bias.

In addition, the drain electrode 155, the gate electrode 151, and thesource electrode 153 may be formed as a single conductive layer, or maybe formed as multiple layers (multilayer) that includes at least twoconductive layers, each made of a different material.

In this case, the semiconductor 130 overlaps the gate electrode 151,interposing the second insulation layer 140 therebetween. Accordingly,the second insulation layer 140 may cover most of the semiconductor 130.Further, the channel region 131 may overlap most of the gate electrode151 in the third direction D3, and the source region 133 and the drainregion 135 may not overlap most of the gate electrode 151 in the thirddirection D3.

Next, an interlayer insulation layer 160 is positioned on the electrodelayer 150. The interlayer insulation layer 160 may be a single layer ora multilayer. When the interlayer insulation layer 160 is formed as asingle layer, the interlayer insulation layer 160 may include aninorganic insulation material, such as a silicon oxide (SiO_(x)), asilicon nitride (SiN_(x)), a silicon oxynitride (SiON), a siliconoxyfluoride (SiOF), and the like. Specifically, the interlayerinsulation layer 160 may include at least one of a silicon nitride(SiN_(x)) and a silicon oxynitride (SiON) to reduce resistance of thesource region 133 and the drain region 135 by injecting hydrogen (H)therein.

When the interlayer insulation layer 160 is formed as a multilayer, thelowest layer may include at least one of a silicon nitride (SiN_(x)) anda silicon oxynitride (SiON) that are capable of introducing hydrogen (H)into the source region 133 and the drain region 135, and a middle layeror an upper layer that includes, for example, a silicon oxide (SiO_(x)),may be formed on the lowest layer. In addition, when the interlayerinsulation layer 160 is formed as a multilayer, another layer thatincludes a material such as a silicon nitride (SiN_(x)) or a siliconoxynitride (SiON) may be further formed on the middle layer thatincludes a silicon oxide (SiO_(x)).

Next, a passivation layer 180 may be positioned on the interlayerinsulation layer 160. The passivation layer 180 may include at least oneof an inorganic insulation material and an organic insulation material,and may be formed as a single layer or multiple layers (multilayer). Inthis case, the passivation layer 180 may have a substantially flat uppersurface.

The interlayer insulation layer 160 and the passivation layer 180include a pixel contact hole 181 exposing the source electrode 153.

Further, a pixel electrode 191 is positioned on the passivation layer180. The pixel electrode 191 may include a transparent conductivematerial, such as indium tin oxide (ITO), indium zinc oxide (IZO), andthe like.

In this case, the pixel electrode 191 is electrically connected with thesource electrode 173 through the pixel contact hole 181, and thus, mayreceive, for example, a data voltage. Consequently, in this exemplaryembodiment, each of the pixel electrode 191 and first electrode 124 iselectrically connected with the source region 133 through the sourceelectrode 153.

Next, referring to FIG. 2B, the switching transistor Qs includes a dataline 171 positioned on the substrate 110, a first insulating layer 111covering the data line 171, a semiconductor 1130 positioned on the firstinsulating layer 111, a second insulation layer 140 covering thesemiconductor 1130, and a drain electrode 1155, a gate electrode 1151,and a source electrode 1153 positioned on the second insulation layer140.

The data line 171 transmits the data signal, and may be positioned atthe same layer as the driving voltage line 172 and the first electrode124 of the driving transistor Qd, as described above. Accordingly, thedata line 171 may include the same material as the driving voltage line172 and the first electrode 124.

The drain electrode 1155 is connected with the data line 171 through acontact hole 1165, a drain region 1135 is connected with the drainelectrode 1155 through a contact hole 1145, and a source region 1133 isconnected with the source electrode 1153 through a contact hole 1143.

A description regarding the substrate 110, the first insulating layer111, and the second insulation layer 140 is the same as the descriptionof the above-described constituent elements, and thus, is omitted.

The semiconductor 1130, the drain electrode 1155, the gate electrode1151, and the source electrode 1153 of the switching transistor Qs mayhave the same structure and material as the above-describedsemiconductor 130, drain electrode 155, gate electrode 151, and sourceelectrode 153 of the driving transistor Qd, and thus, the descriptionthereof is omitted.

Referring to FIG. 2A and FIG. 1 , the gate electrode 151 of the drivingtransistor Qd is connected with the source electrode 1153 of theswitching transistor Qs, and thus, may be supplied with a gate signal.Further, the gate electrode 1151 of the switching transistor Qs iselectrically connected with a gate line 121, and thus, may be suppliedwith the gate signal. In this case, the gate line 121 extends in adirection crossing the data line 171.

According to an exemplary embodiment, the first electrode 124 of thetransistor is electrically connected with the source region 133 via thesource electrode 153. Accordingly, a source voltage, which is a voltageof the source region 133, may be applied to the first electrode 124. Asdescribed, when the source voltage is applied to the first electrode124, a current change rate (i.e., a current slope) in a saturation areais decreased in a voltage-current characteristic graph so that an outputsaturation characteristic of the transistor can be improved. When thetransistor has a superior output saturation characteristic, thetransistor TR becomes more insensitive to undesirable voltagefluctuations of the source region 133 caused by deterioration of variousconnected elements, such as an emission element connected to thetransistor, for example, such that an output current of the transistorTR can be less affected. Thus, the transistor according to the presentexemplary embodiment can be advantageous as a driving transistor of adisplay device such as an organic light emission display, and may alsobe advantageous for forming an external current sensing circuit.

In addition, as described above, because the second insulation layer 140is positioned on the entire surface of the substrate 110, it is possibleto prevent the mobility from being reduced due to an electric fieldinduced between the gate electrode 151 and the semiconductor 130,thereby improving the stability of the transistor.

Although in this exemplary embodiment the driving transistor Qd has thecross-sectional structure shown in FIG. 2A and the switching transistorQs has the cross-sectional structure of FIG. 2B, the cross-sectionalstructures of the transistors are not limited thereto, and the switchingtransistor Qs may also have the cross-sectional structure including thefirst electrode 124, as shown FIG. 2A.

While the above-described FIG. 2A and FIG. 2B are cross-sectional viewsof a portion of the transistor display panel shown in FIG. 1 , a planestructure of the transistor display panel having a cross-sectionalstructure like in FIG. 2A and FIG. 2B is not limited to that of FIG. 1 .FIG. 1 shows a part of the transistor display panel of an organic lightemitting diode display including a driving transistor Qd and a switchingtransistor Qs. However, an exemplary embodiment is not limited to theorganic light emitting diode display, and may be applied to variousdisplay devices such as a liquid crystal display.

Next, a method for manufacturing of the transistor display panel havingthe cross-sectional structure shown in FIG. 2A according to an exemplaryembodiment will be described with reference to FIG. 3 to FIG. 8 .

FIG. 3 to FIG. 8 are cross-sectional views showing a method formanufacturing of a transistor display panel according to an exemplaryembodiment.

First, referring to FIG. 3 , a first conductive material, such as ametal, is deposited on the substrate 110, and then patterned so that thedriving voltage line 172 and the first electrode 124 are formed.

In this case, the first conductive material may be deposited bysputtering and the like, and patterned by using a photosensitivematerial such as a photoresist and a mask.

When the transistor is a transistor for a liquid crystal display (LCD),a first capacitor electrode 128a and the data line 171 of the switchingtransistor Qs, which are integrally connected to the first electrode 124of the driving transistor Qd, may be simultaneously formed by thisprocess.

Next, referring to FIG. 4 , an inorganic material is deposited on thesubstrate 110 having the driving voltage line 172 and the firstelectrode 124 to form the first insulating layer 111, and then thesemiconductor 130 is formed thereon.

In this case, as the inorganic material, for example, a silicon oxide(SiO_(x)), a silicon nitride (SiN_(x)), aluminum oxide (Al₂O₃), hafniumoxide (HfO₃), yttrium oxide (Y₂O₃), and the like may be used, and thefirst insulating layer 111 may be deposited by chemical vapor deposition(CVD).

Further, a semiconductor material, such as zinc oxide (ZnO), zinc-tinoxide (ZTO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide(TiO), indium-gallium-zinc oxide (IGZO), indium-zinc-tin oxide (IZTO),and the like, is deposited on the first insulation layer 111 usingchemical vapor deposition and then patterned using a second mask suchthat the semiconductor 130 is formed.

Next, referring to FIG. 5 , inorganic insulating material is depositedon the substrate 110 having the semiconductor 130 to form the secondinsulating layer 140. In this case, as the inorganic material, forexample, the above-described insulating material may be used, and thesecond insulating layer 140 may be deposited by chemical vapordeposition (CVD).

Referring to FIG. 6 , the first insulating layer 111 and the secondinsulation layer 140 are then etched to form the first contact hole 163and the second contact hole 165, the second insulation layer 140 isetched to form the third contact hole 143 and the fourth contact hole145, and then the source region 133, the drain region 135, and thechannel 131 may be formed.

In this case, the first to fourth contact holes 163, 165, 143, and 145may be simultaneously formed, or the first contact hole 163 and thesecond contact hole 165 may be formed first after the first insulatinglayer 111 is formed, and then the second insulating layer 140 may beformed thereon and the third contact hole 143 and the fourth contacthole 145 may be formed, but the inventive concept is not limitedthereto. Further, the first to fourth contact holes 163, 165, 143, and145 may be formed by at least one of wet etching and dry etching.

In this case, according to this exemplary embodiment, the source region133 and the drain region 135 may be connected by etching only the thirdcontact hole 143 and fourth contact hole 145, and thus, excessiveetching of the semiconductor 130 can be prevented. Accordingly,operating characteristics of the transistor can be improved.

Hydrogen is dispersed to the semiconductor 130 through the third contacthole 143 and the fourth contact hole 145 by performing a plasmatreatment in a hydrogen gas atmosphere to make the source region 133 andthe drain region 135 conductive, and an area not being conductive bybeing blocked by the upper electrode 125 may be formed as the channel131.

Next, referring to FIG. 7 , the second conductive material is depositedon the second insulating layer 140, and then patterned so that theelectrode layer 150 including the drain electrode 155, the gateelectrode 151, and the source electrode 153 is formed.

As the second conductive material, for example, a metal such as copper(Cu), aluminum (Al), silver (Ag), molybdenum (Mo), chromium (Cr),tantalum (Ta), titanium (Ti), and the like, or a metal alloy thereof,may be used, but the inventive concept is not limited thereto.

In this case, the second conductive material may be deposited bysputtering. The second conductive material may be patterned bydepositing a photosensitive material on the second conductive materialand dry etching or dry etching with a mask.

As described, according to the method for manufacturing of thetransistor display panel of this disclosure, the drain electrode 155,the gate electrode 151, and the source electrode 153 may besimultaneously formed by a single process.

When the transistor is a driving transistor Qd for a liquid crystaldisplay (LCD), a second capacitor electrode 128b, which is integrallyconnected to the gate electrode 151, may be simultaneously formed bythis process.

Next, referring to FIG. 8 , the interlayer insulation layer 160 and thepassivation layer 180 covering the electrode layer 150 are sequentiallyformed by chemical vapor deposition and the like. In this case, as amaterial for the interlayer insulation layer 160, for example, aninorganic insulating material such as a silicon oxide (SiO_(x)), asilicon nitride (SiN_(x)), a silicon oxynitride (SiON), and a siliconoxyfluoride (SiOF) may be used, and as a material for the passivationlayer 180, for example, an organic insulating material such as apolyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin,a polyimide resin, an unsaturated polyester resin, a polyphenylene etherresin, a polyphenylene sulfide resin, or benzocyclobutene (BCB) may beused, but the inventive concept is not limited thereto.

Subsequently, the pixel contact hole 181 is formed by etching theinterlayer insulation layer 160 and the passivation layer 180, and thepixel electrode 191 is formed on the pixel contact hole 181, such thatthe transistor display panel having the cross-sectional structure asshown FIG. 2A may be formed.

As described above, according to the method for manufacturing of thetransistor display panel of this exemplary embodiment, since the drainelectrode 155, the gate electrode 151, and the source electrode 153 aresimultaneously formed, the forming step and the etching step foradditional forming the insulating film having a thickness of about 5000Å or more can be omitted, as compared with the conventional method inwhich the drain electrode 155 and the source electrode 153 are formed inlayers different from that of the gate electrode 151.

Accordingly, according to the method for manufacturing of the transistordisplay panel of this exemplary embodiment, the manufacturing processcan be simplified and the number of masks required can be reduced, sothat the productivity can be effectively improved.

Next, display devices including the transistor display panel accordingto an exemplary embodiment of this disclosure will be described withreference to FIG. 9 to FIG. 11 .

FIG. 9 is an equivalent circuit diagram of one pixel of a display deviceaccording to an exemplary embodiment, and FIG. 10 is a cross-sectionalview of a display device according to an exemplary embodiment.

In this case, the display device is an organic light emitting diodedisplay, and may include the transistor according to the above-describedexemplary embodiment. Accordingly, the same description regarding to theabove-described constituent elements will be omitted.

Referring to FIG. 9 along with FIG. 1 , one pixel PX of the displaydevice that includes the transistor display panel according to theexemplary embodiment includes a plurality of signal lines 121, 171, and172, a plurality of transistors Qs and Qd that are connected with theplurality of signal lines 121, 171, and 172, and an organic lightemitting diode OLED.

The transistors Qs and Qd include a switching transistor Qs and adriving transistor Qd.

The signal lines 121, 171, and 172 include a plurality of gate lines 121that transmit a gate signal Sn, a plurality of data lines 171 thattransmit a data signal Dm, and a plurality of driving voltage lines 172that transmit a driving voltage ELVDD.

The gate lines 121 extend in the first direction D1 and aresubstantially parallel to each other, and the data lines 171 extend inthe second direction D2 and are substantially parallel to each other.Although the driving voltage line 172 is shown extending in the seconddirection D2, the driving voltage line 172 may extend in the firstdirection D1 or the second direction D2, or may have a web shapeincluding a portion extending in the first direction D1 and a portionextending in the second direction D2.

Although not shown in the figures, one pixel PX may further include athin film transistor and a capacitor in order to compensate a currentapplied to the organic light emitting element.

The switching transistor Qs includes a control terminal, an inputterminal, and an output terminal. The control terminal is connected tothe gate line 121, the input terminal is connected to the data line 171,and the output terminal is connected to the driving transistor Qd. Theswitching transistor Qs transmits the data signal Dm applied to the dataline 171 to the driving transistor Qd in response to the gate signal Snapplied to the gate line 121.

The driving transistor Qd also includes a control terminal, an inputterminal, and an output terminal. The control terminal is connected tothe switching transistor Qs as the output terminal of the switchingtransistor Qs, the input terminal is connected to the driving voltageline 172, and the output terminal is connected to the organic lightemitting diode OLED. The driving transistor Qd outputs an output currentId, the magnitude of which varies according to a voltage applied betweenthe control terminal and the output terminal.

The storage capacitor Cst is connected between the control terminal andthe input terminal of the driving thin film transistor Qd. In this case,the storage capacitor Cst charges a data signal applied to the controlterminal of the driving thin film transistor Qd, and maintains thecharge of the data signal even after the switching thin film transistorQs is turned off.

The storage capacitor Cst includes the first capacitor electrode 128aand the second capacitor electrode 128b, as shown in FIG. 1 .Particularly, the first capacitor electrode 128a is positioned at thesame layer as the first electrode 124 and is integrally connected to thefirst electrode 124. Further, the second capacitor electrode 128b ispositioned at the same layer as the gate electrode 151 and is integrallyconnected to the gate electrode 151.

The organic light emitting diode OLED includes an anode connected to theoutput terminal of the driving thin film transistor Qd and a cathodeconnected to a common voltage ELVSS. The organic light emitting diodeOLED displays an image by emitting light, the magnitude of which variesdepending on a current of the driving thin film transistor Qd.

The organic light emitting diode OLED may include an organic materialthat uniquely emits one or more of primary colors such as red, green,and blue, and the organic light emitting device displays a desired imagewith a spatial sum of these colors.

The switching thin film transistor Qs and the driving thin filmtransistor Qd may be n-channel field effect transistors (FET) orp-channel field effect transistors. Further, a connection relationshipbetween the switching and driving thin film transistors Qs and Qd, thestorage capacitor Cst, and the organic light emitting diode OLED can bechanged.

The cross-sectional structure shown in FIG. 9 will be described indetail with reference to FIG. 10 . However, the same descriptionregarding the above-described constituent elements will be omitted.

As shown in FIG. 10 , a pixel defining layer 360 is positioned on thepassivation layer 180 and the pixel electrode 191. The pixel defininglayer 360 includes an opening that exposes the pixel electrode 191. Thepixel defining layer 360 may include an inorganic material, such aspolyacrylics, polyimides, and the like.

An emission layer 370 is positioned in the opening of the pixel defininglayer 360 over the pixel electrode 191, and a common electrode 270 ispositioned on the emission layer 370. The pixel electrode 191, theemission layer 370, and the common electrode 270 form the organic lightemitting diode OLED. The pixel electrode 191 may be an anode of theorganic light emitting diode OLED, and the common electrode 270 may be acathode of the organic light emitting diode OLED.

Light emitted from the emission layer 370 may be reflected severaltimes, passed through the substrate 110, and then be emitted downthrough the substrate 110, or may be emitted above the substrate 110without passing through the substrate 110.

Although not shown in the figures, an encapsulation layer may be formedon the common electrode 270 to protect the organic light emitting diodeOLED.

Next, FIG. 11 is a cross-sectional view of a display device according toan exemplary embodiment.

The display device according to the present exemplary embodiment is aliquid crystal display (LCD), and may include the transistor accordingto the above-described exemplary embodiment. Here, the same descriptionregarding to the above-described constituent elements will be omitted.

As shown in FIG. 11 , a liquid crystal layer 3 including liquid crystalmolecules 31 is positioned on the pixel electrode 191.

An insulation layer 210 encapsulating the liquid crystal layer 3 withthe substrate 110 is positioned on the liquid crystal layer 3

The insulation layer 210 may be of a substrate type.

An opposed electrode 280 may be positioned under or over the insulationlayer 210. The opposed electrode 280 may generate an electric field tothe liquid crystal layer 3 with the pixel electrode 191, therebycontrolling the direction of the liquid crystal molecules 31. However,the opposed electrode 280 may be positioned between the substrate 110and the liquid crystal layer 3. The opposed electrode 280 may include atransparent conductive material such as ITO, IZO, and the like. Forexample, a common voltage may be applied to the opposed electrode 280.

Next, alignment layers 21 and 11 are respectively positioned between theliquid crystal layer 3 and the insulation layer 210, and between theliquid crystal layer 3 and the pixel electrode 191. The alignment layers11 and 21 control the initial arrangement of the liquid crystalmolecules 31 when no electric field is generated in the liquid crystallayer 3. The alignment layers 11 and 21 may be adjacent to the liquidcrystal layer 3.

The display device according to the present exemplary embodiment mayfurther include a backlight for supplying light as a light-receivingtype of display device. The back-light may be positioned under thesubstrate 110.

In addition, the transistor display panel according to an exemplaryembodiment may be included in various display devices.

Although certain exemplary embodiments and implementations have beendescribed herein, other embodiments and modifications will be apparentfrom this description. Accordingly, the inventive concept is not limitedto such embodiments, but rather to the broader scope of the presentedclaims and various obvious modifications and equivalent arrangements.

What is claimed is:
 1. A transistor display panel comprising: a drivingvoltage line and a first electrode disposed on a substrate; asemiconductor disposed on the substrate and overlapping the firstelectrode; and an electrode layer overlapping the semiconductor, theelectrode layer comprising a drain electrode, a gate electrode, and asource electrode; wherein: the semiconductor includes a source region, adrain region, and a channel region; all areas of the source region, thedrain region, and the channel region are disposed above and overlap thefirst electrode in a direction perpendicular to the substrate; the firstelectrode and the semiconductor are connected through the sourceelectrode; and the first electrode is disposed between the substrate andthe semiconductor; and the first electrode and the driving voltage lineare disposed in the same layer.
 2. The transistor display panel of claim1, wherein the drain region and the driving voltage line are connectedthrough the drain electrode.
 3. The transistor display panel of claim 1,wherein the source region and the first electrode are connected throughthe source electrode.
 4. The transistor display panel of claim 1,wherein the drain electrode, the gate electrode, and the sourceelectrode are disposed in the same layer.
 5. The transistor displaypanel of claim 1, wherein the first electrode and the driving voltageline are disposed in the same layer.
 6. A transistor display panelcomprising: a driving voltage line and a first electrode disposed on asubstrate; a semiconductor disposed on the substrate and overlapping thefirst electrode; and an electrode layer overlapping the semiconductor,the electrode layer comprising a drain electrode, a gate electrode, anda source electrode; a first insulating layer covering the drivingvoltage line and the first electrode; and a second insulating layercovering the semiconductor, wherein: the first electrode and thesemiconductor are connected through the source electrode; the firstelectrode is disposed between the substrate and the semiconductor; thefirst insulating layer and the second insulating layer comprise a firstcontact hole connecting the first electrode and the source electrode anda second contact hole connecting the driving voltage line and the drainelectrode; and the second insulating layer comprises a third contacthole connecting the source region and the source electrode and a fourthcontact hole connecting the drain region and the drain electrode; thesemiconductor includes a source region, a drain region, and a channelregion; all areas of the source region, the drain region, and thechannel region are disposed above and overlap the first electrode in adirection perpendicular to the substrate; and the first electrode andthe driving voltage line are disposed in the same layer.
 7. Thetransistor display panel of claim 6, wherein the second insulating layeris disposed on an entire surface of the substrate.
 8. A display devicecomprising: a driving voltage line and a first electrode disposed on asubstrate; a semiconductor disposed on the substrate and overlapping thefirst electrode; an electrode layer overlapping the semiconductor, theelectrode layer comprising a drain electrode, a gate electrode, and asource electrode; and a pixel electrode disposed on the electrode layer,wherein: the first electrode and the semiconductor are connected throughthe source electrode; and each of the pixel electrode and the firstelectrode is connected with the semiconductor through the sourceelectrode; and the first electrode is disposed between the substrate andthe semiconductor; the semiconductor includes a source region, a drainregion, and a channel region; all areas of the source region, the drainregion, and the channel region are disposed above and overlap the firstelectrode in a direction perpendicular to the substrate; and the firstelectrode and the driving voltage line are disposed in the same layer.9. The display device of claim 8, further comprising: a first capacitorelectrode disposed on the substrate; and a second capacitor electrodedisposed on the first capacitor electrode, wherein: the first capacitorelectrode is integrally connected with the first electrode; and thesecond capacitor electrode is integrally connected with the gateelectrode.
 10. The display device of claim 8, wherein: the semiconductorcomprises a drain region, a channel, and a source region; the drainregion and the driving voltage line are connected through the drainelectrode; and the source region and the first electrode are connectedthrough the source electrode.
 11. The display device of claim 8, furthercomprising; a first insulating layer covering the driving voltage lineand the first electrode; and a second insulating layer covering thesemiconductor, wherein: the first insulating layer and the secondinsulating layer comprise a first contact hole connecting the firstelectrode and the source electrode and a second contact hole connectingthe driving voltage line and the drain electrode; and the secondinsulating layer comprises a third contact hole connecting the sourceregion and the source electrode and a fourth contact hole connecting thedrain region and the drain electrode.
 12. A display device comprising: adriving voltage line and a first electrode disposed on a substrate; asemiconductor disposed on the substrate and overlapping the firstelectrode; and an electrode layer overlapping the semiconductor, theelectrode layer comprising a drain electrode, a gate electrode, and asource electrode; wherein: the semiconductor includes a source region, adrain region, and a channel region; the source region, the drain region,and the channel region are disposed above and overlap the firstelectrode in a direction perpendicular to the substrate; the firstelectrode and the semiconductor are connected through the sourceelectrode; the first electrode is disposed between the substrate and thesemiconductor; and the first electrode and the driving voltage line aresimultaneously formed by the same process and disposed in a same layer.13. The display device of claim 12, wherein the drain region and thedriving voltage line are connected through the drain electrode.
 14. Thedisplay device of claim 12, wherein the source region and the firstelectrode are connected through the source electrode.
 15. The displaydevice of claim 12, wherein the drain electrode, the gate electrode, andthe source electrode are simultaneously formed by a same process anddisposed in a same layer.
 16. The display device of claim 12, whereinthe gate electrode, the source electrode, and the drain electrode aremade of a same material.
 17. The display device of claim 12, wherein thedriving voltage line and the first electrode are made of a samematerial.
 18. The display device of claim 12, wherein the semiconductorincludes an oxide of at least one of zinc (Zn), indium (In), gallium(Ga), tin (Sn), titanium (Ti), or a combination of a metal including atleast one of zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium(Ti), and an oxide thereof.
 19. The display device of claim 12, whereinthe semiconductor includes at least one of zinc oxide (ZnO), zinc-tinoxide (ZTO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide(TiO), indium-gallium-zinc oxide (IGZO), and indium-zinc-tin oxide(IZTO).
 20. The display device of claim 12, further comprising: a firstinsulating layer disposed on the driving voltage line and the firstelectrode; and a second insulating layer disposed on the semiconductor,wherein: the first insulating layer and the second insulating layercomprise a first contact hole connecting the first electrode and thesource electrode, and a second contact hole connecting the drivingvoltage line and the drain electrode; and the second insulating layercomprises a third contact hole connecting the source region and thesource electrode, and a fourth contact hole connecting the drain regionand the drain electrode.
 21. The display device of claim 20, wherein thefirst insulating layer is a double layer.
 22. The display device ofclaim 20, wherein: the first insulating layer includes a lower layer andan upper layer; and the lower layer includes SiN_(x) and the upper layerincludes SiO_(x).
 23. The display device of claim 20, wherein the secondinsulating layer comprises a silicon oxide layer.
 24. The display deviceof claim 20, wherein: the second insulating layer is disposed betweenthe semiconductor and the gate electrode; and the second insulatinglayer disposed between the gate electrode and the semiconductor does nothave a contact hole.
 25. A display device comprising: a driving voltageline and a first electrode disposed on a substrate; a semiconductordisposed on the substrate and overlapping the first electrode; anelectrode layer overlapping the semiconductor, the electrode layercomprising a drain electrode, a gate electrode, and a source electrode;and a pixel electrode disposed on the electrode layer, wherein: thesemiconductor includes a source region, a drain region, and a channelregion; the source region, the drain region, and the channel region aredisposed above and overlap the first electrode in a directionperpendicular to the substrate; the first electrode and thesemiconductor are connected through the source electrode; the firstelectrode is disposed between the substrate and the semiconductor; eachof the pixel electrode and the first electrode is connected with thesemiconductor through the source electrode; and the drain electrode, thegate electrode, and the source electrode are disposed on a same layer.26. The display device of claim 25, wherein a first capacitor electrodeand a second capacitor electrode form a first capacitor, wherein: thefirst capacitor electrode is overlapped with the semiconductor; and thesecond capacitor electrode is disposed on the electrode layer.
 27. Thedisplay device of claim 25, wherein: the drain region and the drivingvoltage line are connected through the drain electrode; and the sourceregion and the first electrode are connected through the sourceelectrode; and the driving voltage line and the first electrode aredisposed in a same layer.
 28. The display device of claim 25, furthercomprising: a first insulating layer disposed on the driving voltageline and the first electrode; and a second insulating layer disposed onthe semiconductor, wherein: the first insulating layer and the secondinsulating layer comprise a first contact hole connecting the firstelectrode and the source electrode and a second contact hole connectingthe driving voltage line and the drain electrode; and the secondinsulating layer comprises a third contact hole connecting the sourceregion and the source electrode and a fourth contact hole connecting thedrain region and the drain electrode.
 29. The display device of claim25, further comprising a gate line disposed in a same layer with theelectrode layer, wherein the gate line is partially overlapped with thefirst electrode in a direction perpendicular to the substrate.